Interra Design Automation technologies are led by standards-compliant EDA building blocks (EDA Objects), HDL coverage test suites and Memory compiler development system (MC2) and Memory Design Framework (Touchstone).
Our technologies are widely used by major SoC Design Houses and EDA Vendors.
Interra’s technologies accelerate service deployment, reduce development time and improve productivity for VLSI designers, Design Flow Automation teams and EDA tool developers. These technologies also lay the foundation for a talented design pool of engineers who bring significant value to design services
Memory Compiler Development System allows memory designer to define their memory architecture for standard or embedded memories. MC2 can then generate memory instance along with full range of front-end and back-end views. MC2 provides a platform for seamless migration to new processes. By enhancing the overall methodology for the design and distribution of memories, MC2 ensures the reuse of a base design over many generations of sub-micron processes. Numerous users have taken advantage of MC2 capabilities for scaling their memory designs to higher densities, placing memories within their SoC, ASIC or IC designs, and making their memory design process more efficient.
Touchstone (Memory Design Engine) is an automated methodology for Memory Design. Easily programmable, it provides a user-friendly platform to describe memories. It supports various characterization schemes, and can be integrated with MC2 (Interra’s Memory Compiler Development System)
Interra’s EDA front-end technologies enable accelerated development of custom automation solutions for VLSI design.
Interra markets analyzers for Verilog, SystemVerilog, VHDL, UPF, CPF, Spice and several other EDA standards. Latest standard compliant and easy to use building blocks from Interra Systems enable users to reduce time-to-market by saving a significant amount of development time.
Interra’s customers include CAD groups of SoC companies, top-tier EDA vendors and EDA startups. EDA Tools that integrate Interra’s EDA Objects are in production-use on thousands of chip designs. Interra ensures its front-ends keep pace with language enhancements, capacity and quality requirements. Interra also provides EDA and CAD Services to Semiconductor Industries, which leverage Interra’s EDA technologies and expertise
Beacon test suites from Interra Systems characterize EDA tools for compliance and coverage across HDL/HVL language constructs and styles. Conforming to industry accepted definition and interpretation of language and synthesis semantics. Interra offers support for various EDA Standards including Verilog-RTL subset, VHDL-RTL subset, SystemVerilog, VHDL-2008, Mixed Language and PSL.
|Memory Design Platform|
|MC2 - Memory Design Platform||Memory Development System for standard and embedded memories|
|TouchStone - Automating Memory Design||Characterization Engine to provide accurate timing and power models for simulation, verification, and synthesis|
|Cheetah - Verilog, SV Front-End
||Complete language front-end for System Verilog applications. Provides access to the parse tree through APIs|
|Jaguar - VHDL Front-End
||Complete language front-end to VHDL applications. Provides access to the parse tree through APIs|
|MixedHDL - Mixed Language Design Elaborator
||Allows analysis of mixed designs that contain Verilog, SystemVerilog and VHDL.|
|NOM - Netlist Front-End||Language independent front-end for netlist applications supporting Verilog, VHDL, and EDIF 200 formats|
|Other Analyzers||Analysis of SPICE, UPF, CPF, SLF, SDF, DSPF/RSPF, VCD, SPEF, SAIF, and GDSII. EDA applications can quickly access data defined in standard languages using APIs|
|HDL Test Suites|
|Beacon - HDL/HVL Test Suites||Family of test suites for RTL-Verilog, RTL-VHDL, Verilog-2001, Mixed Verilog VHDL, System Verilog, System Verilog Assertions, and PSL|
|Concorde - Fast Synthesis/Elaborator||Fast RTL Synthesis/elaboration for System Verilog, Verilog, VHDL, and mixed designs. Quick synthesis can be used for verification, acceleration, and estimation purposes|